1. Field of the Invention
The present invention relates to a semiconductor device having a metal wiring structure and a method of manufacturing the semiconductor device including the metal wiring structure. More particularly, the present invention relates to a semiconductor device including a metal wiring structure electrically connected to a plug and a method of manufacturing the semiconductor device having the metal wiring structure.
2. Description of the Related Art
To meet varied demands, semiconductor devices have been developed that exhibit high response speeds, high reliabilities, high integration degrees, etc. To improve the response speed of the semiconductor device, memory cells are integrated on one chip to thereby reduce the design rule of the semiconductor devices. Accordingly, conductive wirings of more modern semiconductor devices typically have multi-layer, three-dimensional structures.
In such semiconductor devices, a contact or a plug is generally provided so as to connect one layer of conductive wiring to another layer of conductive wiring or electrically connect between conductive wiring regions of a substrate. Thus, the contact or the plug reduces a contact resistance between conductive wirings or between conductive wiring and the substrate. The contact or the plug typically includes a barrier layer and a conductive layer. The conductive layer may include doped polysilicon or a metal such as tungsten (W). The conductive wiring of metal is formed on the contact or the plug so that the conductive wiring is electrically connected to a lower conductive wiring or a contact region of a substrate.
FIG. 1 is a block diagram illustrating a conventional method of forming a metal wiring electrically connected to a contact plug, and FIG. 2 is a cross sectional view illustrating a semiconductor device including the metal wiring formed in the process of FIG. 1.
Referring to FIGS. 1 and 2, after an insulation layer 14 is formed on a substrate 10, the insulation layer 14 is partially etched to form contact holes that expose a gate electrode (not shown) and a portion of substrate 10, respectively in step S10.
In step S20, a cleaning process is performed, and then barrier layers 16 are formed on the gate electrode, the exposed portion of the substrate 10 and sidewalls of the contact holes.
After a polysilicon layer is formed on the barrier layers 16 to fill up the contact holes, the polysilicon layer is partially removed by a chemical mechanical polishing (CMP) process to thereby form plugs 18 in the contact holes in step S30.
In step S40, a tungsten layer is formed on plugs 18 and the insulation layer 14, and then an etching mask is formed on the tungsten layer. In step S50, the tungsten layer is etched by a dry etching process using the etching mask so that tungsten wirings 20 are formed on the full-height plugs 18, respectively.
Below design rules of about 13 μm, however, the plug 18 has an area substantially identical to that of metal wiring 20. Any alignment error of an etching mask relative to the plug 18 during formation of the metal wiring can reduce the effectiveness of the semiconductor device. That is, when the etching mask is incorrectly positioned with respect to the plug 18, the plug 18 may be damaged in the etching process for forming the metal wiring, thereby generating a recess D as shown in FIG. 2. The recess D is typically generated due to an etching rate difference between the plug 18 and the metal wiring during the etching process.
When the recess D is formed on the plugs 18, a contact failure between the plug 18 and the metal wiring may occur, thereby deteriorating the electrical characteristics of a semiconductor device between the plugs 18 and the metal wiring.